|European Case Law Identifier:||ECLI:EP:BA:2004:T014003.20040929|
|Date of decision:||29 September 2004|
|Case number:||T 0140/03|
|IPC class:||H01L 23/50|
|Language of proceedings:||EN|
|Download and more information:||
|Title of application:||Intergrated circuit package|
|Applicant name:||W.L. GORE & ASSOCIATES, INC.|
|Relevant legal provisions:||
|Keywords:||Remittal (yes) - claims substantially amended|
Summary of Facts and Submissions
I. European patent application No. 96 117 537.9 was refused in a decision of the examining division dated 10 September 2002 on the ground that the subject matter of claims 1 to 7 filed with the letter dated 6 March 2002 did not involve an inventive step having regard to the prior art documents
D1: C. R Hodges et al., "Design of Mixed Signal MCM-Ds using Silicon Circuit Boards", Proceedings of the IEEE Multi-Chip Module Conference, Santa Cruz, 31. January to 2 February 1995, pages 130 to 135;
D2: US-A-5 402 318; and
D3: US-A-5 034 801.
II. The appellant (applicant) lodged an appeal together with a statement of the grounds of appeal on 8 November 2002, paying the appeal fee the same day.
III. The appellant requests that the decision under appeal be set aside and a patent be granted on the basis of the following documents:
Claims 1 to 4 filed 8 November 2002 with the statement of the grounds of appeal;
pages 1, 4, 4a as filed with the letter dated 6. March 2002,
pages 2, 3, and 5 to 19 as originally filed;
Drawings sheets 1/7 to 7/7 as originally filed.
As an auxiliary measure, oral proceedings are requested.
IV. Claim 1 under consideration reads as follows (emphasis added by the Board to indicate the features added with respect to claim 1 which formed the basis for the decision under appeal):
"1. An integrated circuit package (10) for housing an integrated circuit chip (22) and providing electrical connectivity of data signals and voltage signals between the integrated circuit chip (22) housed therein and an electronic component, the package (10) comprising:
a carrier substrate (14) having a first surface (16) including a die attach region (18) and a signal layer region (20);
an integrated circuit chip (22) affixed to the die attach region (18), the integrated circuit chip (22) including a plurality of bonding pads (24);
at least three conductive layers (28, 30, 32, 36) on the signal layer region (18) of the substrate (14) for conducting electrical signals, the conductive layers comprising at least a first voltage layer (28) adjacent to the substrate (14) for providing a first reference voltage signal to the integrated circuit chip (22), a second voltage layer (30) for providing a second reference voltage signal to the integrated circuit chip (22), and a single signal layer (32), the first voltage layer (28) comprising a reference ground layer adjacent to the substrate for providing a ground signal to the integrated circuit chip (22) and the second voltage layer comprising a reference voltage layer closely coupled to the reference ground layer thereby providing a predetermined level of decoupling capacitance therebetween;
a plurality of bond wires (44) having a predetermined length, each bond wire (44) electrically connecting a single bonding pad (24) of the integrated circuit chip (22) to a single bonding pad (42) of the signal layer (32) each bond wire (44) being disposed parallel one to each other to route all of the data signals on the single signal layer (32) to minimize the length of the bond wires, the bond wire (44) inductance being in a range from about less than 1 nH to about greater than 0.25 nH;
at least first and second dielectric layers (38, 40), the at least first dielectric layer (38) being disposed between the first and second voltage layers (28, 30) and comprising filled polytetrafluoroethylene having a dielectric constant in a range from 8 to 25, and the at least second dielectric layer (40) being disposed between the second voltage layer (30) and the signal layer (32), and comprising at least in part cyanate ester impregnated expanded polytetrafluoroethylene having a dielectric constant in a range from 2.5 to 3.2; and
a plurality of electrical connections (46, 48) for interconnecting the chip bonding pads (24, 42) with the electronic component by way of at least one of the conductive layers (28, 30, 32) for conducting electrical signals therebetween."
V. In the decision under appeal, the examining division held that the subject matter of claim 1 did not involve an inventive step having regard to documents D1 and D2. The added feature of claim 2 specifying that the second dielectric layer comprises cyanate ester impregnated expanded polytetrafluoroethylene (PTFE) was considered obvious having regard to document D3.
VI. The appellant (applicant) presented essentially the following arguments in support of his request:
(a) None of the cited documents disclose or suggest PTFE having a high dielectric constant, as in the claimed device for the first dielectric layer.
(b) The relevance of document D3 is contested, since it relates to a different type of device than that defined in claim 1.
Reasons for the Decision
1. The appeal complies with Articles 106 to 108 and Rule 64 EPC and is therefore admissible.
2. Claim 1 corresponds to a combination of independent claim 2 as filed and the features disclosed on page 11, line 35 to page 12, line 11 and page 12, lines 13 to 16 of the application as filed. Therefore, claim 1 as amended meets the requirements of Article 123(2) EPC.
3. With respect to claim 1 which was considered not to meet the requirement of inventive step in the decision under appeal, the subject matter of claim 1 presently under consideration further specifies
(A) that the first dielectric layer comprises filled polytetrafluoroethylene (PTFE) having a dielectric constant in a range from 8 to 25; and
(B) that the second dielectric layer comprises at least in part cyanate ester impregnated expanded PTFE having a dielectric constant in a range from 2.5. to 3.2.
Feature (A) was not previously claimed, whereas feature (B) was discussed in the decision under appeal in connection with claim 2 (cf. item V above).
4. In the present case, the appellant no longer seeks grant of a patent including the subject matter as rejected by the examining division, but has filed an amended text for claim 1. Furthermore, the appellant has entirely based the arguments in favour of inventive step on the new features (A) and (B) and has not contested the reasoning given in the decision under appeal with regard to the rejected claim 1.
5. Feature (A) was not previously claimed and appears to play a crucial role in the assessment of inventive step, since, as the appellant pointed out in the statement of the grounds of appeal, it does not appear that any of the cited prior art documents disclose this feature (cf. item VI(a) above). The question therefore arises whether or not the feature (A) was taken into account by the search division when the European Search Report was drawn up.
Although the above features (A) and (B) have a basis in the application as filed (cf. item 2 above), the amendments proposed in claim 1 nevertheless require substantial further examination in particular in relation to the requirement of inventive step.
6. Under these circumstances, it is appropriate that the case should be remitted to the examining division in accordance with Article 111(1) EPC (cf. T 63/86, OJ EPO 1988, 224).
The Board also refers to decision T 1032/92, where it was stated that the filing of a new request for the first time in the statement of the grounds of appeal, as in the present case, inevitably leads to undesirable procedural delay.
For these reasons it is decided that:
1. The decision under appeal is set aside.
2. The case is remitted to the department of the first instance for further examination of the application on the basis of the appellant's request as set out in the statement of the grounds of appeal.