|European Case Law Identifier:||ECLI:EP:BA:2006:T019503.20061011|
|Date of decision:||11 October 2006|
|Case number:||T 0195/03|
|IPC class:||H04N 7/24|
|Language of proceedings:||EN|
|Download and more information:||
|Title of application:||Data deinterleaver om a digital television signal decoding system|
|Applicant name:||THOMSON CONSUMER ELECTRONICS, INC.|
|Relevant legal provisions:||
|Keywords:||Remittal for further prosecution|
Summary of Facts and Submissions
I. This appeal is against the decision of the examining division to refuse European patent application No. 95 118 343.3.
II. The following documents will be referred to in the present decision:
D1: US-A-5 063 533
D2: EP-A-0 582 827.
III. The examining division held that the subject-matter of claims 1 to 6 according to the then main and auxiliary requests lacked an inventive step with respect to D1, taken to represent the closest prior art.
IV. In the statement of grounds of appeal dated 28 January 2003 the appellant requested that the decision be set aside and a patent be granted based on an amended claim 1 filed with the same letter, claims 2 to 6 remaining unchanged. The claims according to the auxiliary request on which the examining division had decided were maintained and re-filed.
V. In a communication from the Board the opinion was expressed that the examining division's argumentation in the decision under appeal appeared convincing.
VI. Oral proceedings before the Board were held on 11 October 2006. The appellant withdrew all previous requests and filed amended claims 1 to 5 according to a new single request.
VII. Claim 1 read:
"Apparatus for receiving a signal representative of interleaved digital video data consisting of data blocks, comprising an input processor (10-14) having an input for receiving said signal representative of interleaved digital video data and for providing an interleaved data output; an output signal processor (38-35) for processing a deinterleaved output signal, and a deinterleaving network (18) interposed between said input processor and said output signal processor, wherein said deinterleaving network (18) contains a single memory unit (35),
characterized in that
said deinterleaving network (18) performs one of the two different deinterleaving algorithms Forney and Ramsey on said interleaved data output to produce said deinterleaved output signal, and comprises a first memory controller (20) controlling read and write addressing of said single memory unit (35) to implement a first one of said deinterleaving algorithms after receiving said data blocks; a second memory controller (25) controlling read and write addressing of said single memory unit (35) to implement the other deinterleaving algorithm after receiving said data blocks; and a source of deinterleaving control signal for disabling one or the other of said first and second memory controllers (20, 25) to dispose the single memory unit (35) to implement a given one of said distinct and different deinterleaving algorithms after receiving said data blocks, wherein only a single deinterleaving algorithm is operable at a time based on the deinterleaving control signal, further comprising a synchronizer (27) receiving said interleaved data and for providing synchronization signals to synchronizing inputs of said first and second memory controllers (20,25) for synchronizing said read and write addressing from said interleaved data."
Claims 2 to 5 were dependent on claim 1.
VIII. The appellant requested that the decision under appeal be set aside and a patent be granted on the basis of claims 1 to 5 submitted at the oral proceedings.
IX. At the end of the oral proceedings the Board announced its decision.
Reasons for the Decision
1. Present claim 1 has been amended during the appeal proceedings. Compared with the claims in the version before the examining division it now additionally comprises the features of previous dependent claim 5 (concerning the synchronizer 27) and a feature taken from the description (the deinterleaving algorithms implementing the Forney and Ramsey functions; cf. column 2, lines 54 to 56). The synchronizer features were at least formally considered by the examining division, which held that "claims 2-5 relate to well known ways of implementing a deinterleaver". The appellant has however argued that the two newly added features are interrelated. According to the appellant, block interleavers, as shown in D1, might provide data synchronization signals from the interleaved data. Convolutional interleavers implementing the Forney and Ramsey algorithms, however, extracted synchronization signals from the deinterleaved data, as demonstrated by figure 1 of D2. It was therefore not obvious to provide synchronization signals to the memory controllers implementing the Forney or Ramsey algorithms from the interleaved data, as set out in claim 1.
2. The Board notes that the amendments made have changed the invention as claimed considerably. Originally it was concerned with an apparatus capable of performing different deinterleaving algorithms. Now, its onus has shifted to the problem of synchronizing data in convolutional interleavers. Since the primary task of the Boards of Appeal is to examine appeals and the examining division has not yet had an opportunity to assess this considerably changed subject-matter, the case is remitted to the examining division for continuation of the examination on the basis of the present set of claims (Article 111(1) EPC).
For these reasons it is decided that:
1. The decision under appeal is set aside.
2. The case is remitted to the department of the first instance for further prosecution.