|European Case Law Identifier:||ECLI:EP:BA:2017:T185913.20171212|
|Date of decision:||12 December 2017|
|Case number:||T 1859/13|
|IPC class:||H01L 29/786|
|Language of proceedings:||EN|
|Download and more information:||
|Title of application:||Thin film transistor, method of manufacturing the same and flat panel display device having the same|
|Applicant name:||Samsung Display Co., Ltd.|
|Relevant legal provisions:||
|Keywords:||Amendments - extension beyond the content of the application as filed (no)
Inventive step - (yes)
Summary of Facts and Submissions
I. The appeal is against the decision of the Examining Division refusing the European patent application No. 09 164 894.9 on the grounds that claim 1 of the Main request as well as of the First and Third Auxiliary requests before it did not involve an inventive step (Articles 52(1) and 56 EPC), and that claim 1 of the Second Auxiliary request lacked clarity (Article 84 EPC).
II. The Appellant (Applicant) requested that the decision of the Examining Division be set aside and a patent be granted according to the Main Request or according to Auxiliary request I. Both requests were filed with the grounds of appeal.
III. From the documents cited by the Examining Division, the following are relevant for the present decision:
D4: EP 1 981 085 A1
D5: WO 2008/069056 A1
IV. In a communication pursuant to Article 15(1) of the Rules of Procedure of the Boards of Appeal (RPBA) which was annexed to the summons to oral proceedings, the Board raised objections regarding lack of novelty (Article 54(1) EPC) and added subject matter (Article 123(2) EPC) against claim 1 of the Main request and indicated that the Auxiliary request I appeared to fulfill the requirements of the EPC.
V. As a reaction to the Board's communication, the Appellant withdrew its Main request on file and resubmitted Auxiliary request I as Main and sole request.
VI. Following the Appellant's reaction, the Board cancelled the oral proceedings and issues its decision in writing.
VII. The Appellant requests that the decision under appeal be set aside and that a patent be granted in the following version:
Claims 1-10 filed with letter dated 10 October 2017;
Pages 1-11 filed with letter dated 10 November 2017
Drawings: sheets 1-12 as originally filed.
VIII. Claim 1 of the Main request is worded as follows:
A method of manufacturing a thin film transistor, comprising:
forming a gate electrode (12) on a substrate (10);
forming a gate insulating film (13) on the gate electrode (12);
forming an activation layer (14) comprising a compound semiconductor oxide, on the gate insulating film (13);
forming a passivation layer (15) of an inorganic oxide which has a band gap equal or below 3.37 eV, preferably equal or below 3 eV adapted to absorb external light on the activation layer (14), wherein the inorganic oxide comprises elements that are also comprised in the compound semiconductor oxide; and
forming source and drain electrodes (16a, 16b) on the passivation layer in contact with the activation layer (14).
Reasons for the Decision
1.1 Claim 1 is a combination of original claims 10 and 16 with additional features coming from the originally filed description (paragraphs  and  of the published application).
1.2 The last feature in claim 1 (forming source and drain electrodes (16a, 16b) on the passivation layer in contact with the activation layer (14)) was present in an earlier version of the claims and was objected to by the Examining Division in the summons to the first-instance oral proceedings. The Examining Division considered this feature to be an unallowable intermediate generalisation because it defined that the source and drain electrodes were in contact with the activation layer without mentioning the contact holes in the passivation layer.
1.3 The Board notes that in original claim 10 and in paragraph  of the original description there is a definition of the source and drain electrodes contacting the activation layer without any mention of contact holes in the passivation layer. Claim 1, thus, meets the requirements of Article 123(2) EPC.
1.4 Regarding the dependent claims:
- claim 2 finds basis in original claim 12;
- claim 3 corresponds to original claim 13;
- claims 4 and 5 find basis in original claim 15;
- claim 6 corresponds to original claim 19;
- claim 7 corresponds to original claim 20;
- claim 8 finds basis in paragraph  of the original description;
- claim 9 finds basis in paragraph  and Figure 1 of the original application;
- claim 10 finds basis in paragraph  and Figure 1 of the original application.
1.5 The Board is satisfied that the requirements of Article 123(2) EPC are met.
2. Patentability (Article 52(1) EPC)
2.1 The claimed invention relates to a method of manufacturing thin film transistors (TFT).
2.2 Closest prior art and differences
2.2.1 The selection of D5 as closest prior art by the Examining Division was not contested by the Appellant and the Board does not see any reason to differ.
2.2.2 D5 discloses (see Figure 1, abstract and page 8, line 10 - page 10, line 8) a method of manufacturing of a TFT comprising forming successively:
- a substrate (1);
- a gate electrode (2) on the substrate;
- a first insulating film (3), corresponding to the gate insulating film of claim 1, on the gate electrode;
- an oxide semiconductor/channel layer (4), corresponding to the activation layer of claim 1, on the gate insulating film;
- a second insulating film (5), corresponding to the passivation layer of claim 1, directly on the activation layer; and
- source (6) and drain (7) electrodes on the passivation layer in contact with the activation layer.
2.2.3 Regarding the materials used for the layers, D5 further discloses:
- For the activation layer, a compound semiconductor oxide, see page 8, lines 10 - 19 (In, Zn, O and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si and Ge) and page 11, line 1, (the main embodiment specifying InGaZnO). Further combinations of materials are disclosed in pages 20 and 21, especially lines 24-27 on page 20 (In-Zn-Ga-Mg oxide, Sn-In oxide, In-Ga oxide, Zn-Ga oxide, Sn-In-Zn oxide).
- For the passivation layer, an inorganic oxide layer (page 9, lines 12-15). In all embodiments it is silicon oxide (SiOx, page 11, lines 7 - 10 for example).
2.2.4 Compared to D5, the method of claim 1 comprises two additional features:
- the passivation layer is of an inorganic oxide which has a band gap equal or below 3.37 eV adapted to absorb external light;
- the inorganic oxide [of the passivation layer] comprises elements that are also comprised in the compound semiconductor oxide [of the activation layer].
2.2.5 Regarding the first distinguishing feature, there is no mention of any band gap of any material in D5. It is generally known that the band gap of SiO2 is about 8,9 eV and of SiOx in general it is at least 6 eV.
2.2.6 Regarding the second distinguishing feature, in D5 the passivation layer is made of SiOx. There is a mention of Si as a possible choice of an element of the activation layer, but this is in the general part, where no material for the passivation layer is mentioned. In the various embodiments where the manufacture of a passivation layer consisting of SiOx is described, the activation layer is made of InGaZnO (page 11, line 1). There is no single embodiment with an explicit disclosure of common elements between the activation and the passivation layer.
2.3 Technical Problem, Solution and Obviousness
2.3.1 The two identified distinguishing features address two different, unrelated, technical problems and will be assessed separately with respect to inventive step. This is also the least favorable case for the Appellant.
2.3.2 Regarding the first distinguishing feature, when the passivation layer is made of an inorganic oxide with a band gap equal or below 3.37 eV, it absorbs external light. In this way, external light does not reach the activation layer and deterioration of transistor's transfer properties is avoided (see also paragraphs  -  of the application).
The problem of how to protect the activation layer from external light is known in the art of manufacturing TFTs, especially when they are to be used in displays (i. e. they are transparent). This problem is conventionally solved by making the activation (semiconductor) layer of a material with a band gap sufficiently large so that it will not absorb any light. This solution is described in document D4 (the only available prior art document mentioning band gaps), where the activation layer is made of a material having a band gap over 3eV (or 3.2 eV or even 3.4 eV) so that absorption of light is avoided (paragraphs , , , ).
In this solution, however, the external light still reaches the activation layer and there is always the risk that some light is absorbed, depending on the selection of material for the activation layer (see also paragraph  of the application). This solution would, thus, limit the selection of materials for the activation layer to materials with a band gap sufficiently large in order to exclude any light absorption. By contrast, in the claimed method, since the external light is absorbed by the passivation layer, there is no light reaching the activation layer, providing better protection. At the same time, the band gap of the material of the activation layer itself is not important, permitting a larger selection of possible materials.
The skilled person starting from D5, would not find any hints to the solution of the claimed method since the only available solution in the state of the art (D4) teaches towards a different direction. This feature is, therefore, not obvious.
2.4 For this reason, the Board concludes that claim 1 of the Main request involves an inventive step within the meaning of Article 56 EPC.
3. The description has been adapted to the new claims and documents D5 and D6 are also cited therein.
4. The Board is, therefore, satisfied that the application meets the requirements of the EPC and a European patent should be granted under Article 97(1) EPC.
For these reasons it is decided that:
1. The appealed decision is set aside.
2. The case is remitted to the department of the first instance with the order to grant a patent in the following version:
Claims 1-10 filed with letter dated 10 October 2017;
Pages 1-11 filed with letter dated 10 November 2017;
Drawings: sheets 1-12 as originally filed.