|European Case Law Identifier:||ECLI:EP:BA:1989:T017086.19890302|
|Date of decision:||02 March 1989|
|Case number:||T 0170/86|
|IPC class:||H03K 17/693|
|Language of proceedings:||EN|
|Download and more information:||
|Title of application:||Input circuit with plurality of channels|
|Applicant name:||Fujitsu Ltd.|
|Relevant legal provisions:||
|Keywords:||Inventive step (no)|
Summary of Facts and Submissions
I. European patent application No. 83 301 772.6 (publication No. 0 091 265) was refused by decision of the Examining Division dated 07.01.1986.
II. That decision was based on Claims 1 and 2 filed with letter dated 08.08.1985. The subject-matter of Claim 1 was not considered to be novel and the subject-matter of Claim 2 not to involve an inventive step with respect to the prior art disclosed in the following documents:
Dl: Rundfunk technische Mitteilungen, Vol. 20, No. 6, December 1976, pages 247-253; and
D2: IBM Technical Disclosure Bulletin, Vol. 9, No. 9, February 1967, pages 1234, 1235.
III. The Appellant (Applicant) lodged a Notice of Appeal against this decision on 04.03.1986 and paid the appeal fee on the same day. A Statement of Grounds was filed together with a new single independent Claim on 12.05.1986.
IV. On 28.10.1988 the Board issued a Communication in which it expressed the provisional opinion that the subject-matter of the single independent Claim did not appear to involve an inventive step in view of documents D2 and Dl.
V. Oral Proceedings were held on 02.03.1989. During the Oral Proceedings the Appellant filed a new Claim and requested that the decision under appeal be set aside and a patent be granted on the basis of that claim.
The Appellant also requested reimbursement of the appeal fee and, subsidiarily, remittal of the case to the Examining Division.
The single independent Claim reads as follows:
"1. An input circuit (11') for receiving an input signal and transferring the same to an internal circuit (17), the input circuit comprising a plurality of selectively actuable channels (12'-0---12'-n), each of the channels comprising an input terminal (14-0---14-n) for receiving the input signal; an output terminal connected to the internal circuit (17), the output terminal of each transfer channel being connected to a common node (n) from which transferred signals are supplied to the internal circuit (17); and a transistor switch (21-0---21-n) connected between the input and output terminals and which is turned conductive in response to a respective channel selection signal whereupon signals can be passed from the input terminal to the output terminal, the arrangement being such that when any transfer channel is selected, the remaining transfer channels are non-selected; characterised in that the input circuit is mounted on a one-chip microcomputer and the channels comprise substantially electrically isolated transfer channels; in that each transistor switch consists of a conductor (13-0---13-n) having first and second ends for transferring the input signal from the first end to the second end, a first transistor (21-0---21-n) connected between the input terminal and the first end of the conductor (13-0---13-n); a second transistor (22-0---22-n) connected between the second end of the conductor and the output terminal; and a third transistor (23-0---23-n) connected to the conductor (13-0---13-n) at a position between the first and second transistors, the arrangement being such that the third transistor (23-0---23-n) is conductive to clamp the voltage of the conductor (13-0---13-n) at a predetermined constant voltage level when the first and the second transistors are non-conductive; the first and second transistors (21-0, 22-0---21-n, 22-n) of each channel being connected to each other via respective common gate leads (24-0---24-n) to which the channel selection signal is applied to turn the selected transfer channel conductive, the gate of the respective third transistor receiving the logical complement of the channel selection signal; and in that the gate leads and the conductors are arranged parallel with each other, each gate lead being sandwiched by the neighbouring pair of the conductors."
VI. The Appellant's submissions can be summarised as follows :
The input circuit specified in the Claim is intended for use in combination with a one-chip microcomputer. Problems arise in such a circuit when it is desired to increase the number of channels because of crosstalk between the channels and of through-talk through the inactive channels. The invention intends to solve both these problems. The problem of through-talk is not mentioned either in Dl or D2. It appears therefore that the through-talk problem was not recognised before the invention was made. Since the invention solves a new unrecognised problem it cannot be considered as obvious. Furthermore, even if the through- talk problem was known, Dl would be dismissed as irrelevant by the skilled person since it does not address the through-talk problem. Dl lies in a different technical field from that of the invention. In fact the invention lies in the micro-computer field since, as specified in the Claim, the input circuit is mounted on a one-chip microcomputer. By contrast Dl lies in the radio and television field as appears from its title and summary which refer to studio quality data, sound and television broadcasting organisations and sound-control installations.
In view of the fact that the field of the invention is the micro-computer field, the field of radio and television would not appear relevant to the skilled person. Thus for this reason he would not consider Dl.
D2 does not appear to refer to the crosstalk problem. Dl refers to this problem but the circuit suggested therein comprises six transistors while the invention only uses three transistors for each channel. There is no suggestion in Dl that the number of transistors could be halved.
Furthermore there is no suggestion, either in Dl or in D2, which could lead to the sandwich arrangement of the conductors according to the invention. Thus, even ìf the skilled person would think of combining D2 and Dl, he would not arrive at the claimed invention.
Regarding the request for refund of the appeal fee, the Appellant observes that the application had been rejected after the first Communication from the Examining Division, no other communication or advice having been received by the Appellant after his reply to the first Communication. This seems to be contrary to the procedure set out in the Guidelines C-VI 4.3. The Appellant stresses that he had filed three pages of comments in reply to the first Communication and that he thought to have answered all objections raised therein. Furthermore, in its Decision, the Examining Division referred to "time division multiplex" in relation to Dl, this point having not been raised in the first Communication. Thus the Appellant had not been able to appreciate the significance of this question and to comment on it.
In view of the great importance given by the Board to D2, which has not been seriously discussed with the Examining Division, remittal to the first instance seems justified.
Remittal is also justified in order to give the Appellant the opportunity to discuss the "time division multiplex" question with the Examining Division.
Reasons for the Decision
1. The appeal complies with Articles 106 to 108 and Rule 64 EPC and is, therefore, admissible.
2. The features specified in the present single claim appear to be disclosed in the originally filed application documents (see in particular the description on page 4, lines 4-8 and from page 4, line 24 to page 5, line 9 and Claims 1, 3, 4 and 6). Thus the amended Claim meets the requirements of Article 123(2) EPC.
3. Novelty The subject-matter specified in the Claim does not appear to be disclosed in any of the cited prior art documents. Thus the subject-matter of the Claim is considered to be novel.
4. Inventive step
4.1. The Board regards D2 as disclosing the prior art closest to the subject-matter of the Claim. This closest prior art is constituted by an analog multiplexer as input circuit to an analog-to-digital converter, and corresponds to the pre- characterising part of the Claim.
4.2. Starting from D2 the skilled person would recognise that problems due to crosstalk between the channels and through- talk through the cutoff (inactive) channels are present in the analog multiplexer described therein. This is supported by Dl which relates to a switch suitable for use in an analog multiplexer (see the summary) and refers to crosstalk suppression (Nebensprech-dämpfung) and through- talk suppression (Sperr- or Über-sprechdämpfung) problems (see in particular page 250, right-hand column, last three lines and page 251, left-hand column, first nineteen lines).
4.3. It would then be obvious to the skilled person to use the switch described in Dl to solve the problems defined above. The switch according to Dl comprises two parallel transfer channels, each of which consists of a conductor having first and second ends, a first transistor connected between the input terminal and the first end of the conductor, a second transistor connected between the second end of the conductor and the output terminal, and a third transistor connected to the conductor at a position between the first and second transistors, the arrangement of each transfer channel being such that the third transistor is conductive to clamp the voltage of the conductor at a predetermined constant voltage level when the first and the second transistors are non-conductive, the first and second transistors of each channel being connected to each other via respective common gate leads to which the channel selection signal is applied to turn the selected transfer channel conductive, the gate of the respective third transistor receiving the logical complement of the channel selection signal.
In replacing each switch of the multiplexer according to D2 by the switch described in Dl the skilled person would realise that, for this purpose, the switch of Dl can be simplified by using only one of the pair of parallel transfer channels it comprises if only transmission of unbalanced signals is required, as is the case with the multiplexer of D2.
4.4. Having done this the skilled person would then have to specify how the circuit should be implemented. It is common to implement electronic circuits in integrated form and thus this appears obvious to the skilled person, especially in view of the hint in Dl of the possibility of implementing the switch in integrated form. It is furthermore well known that crossings between conductors should be avoided as far as possible in an integrated circuit and that the chip area used by the conductors should be kept to a minimum. With these principles in mind it is obvious to the skilled person that the gate leads, which connect the gates of the first and second transistors in each channel, and the conductors, which also connect said two transistors in each channel, have to be arranged along parallel lines on the chip. To avoid crossings between such lines it is necessary to have each gate lead sandwiched by a neighbouring pair of conductors.
4.5. The feature that the input circuit is mounted on a one-chip microcomputer does not seem to be related to the other features specified in the Claim. Thus the Board considers that this feature could be disregarded when assessing inventive step. This is confirmed by the description which states on page 4, lines 24-30, that the internal circuit mounted on the chip is not essential to the invention.
Furthermore the Board notes that, according to the description of prior art given in the application in relation to Fig. 1, this feature was known in combination with the other features disclosed in D2. Thus, according to the Applicant himself this feature would be obvious to the skilled person.
4.6. Thereby the skilled person would arrive in an obvious way at an input circuit falling within the scope of the Claim.
4.7. The arguments presented by the Appellant in relation to the question of inventive step do not appear to be convincing for the following reasons:
It is clear from Dl that through-talk was known to constitute a problem in selection switches. Thus the problem addressed by the invention is neither new nor un- recognisable.
Since the input circuit of the invention is in fact an analog multiplexer, it cannot be considered that Dl lies in a different technical field because this document specifically refers to this technical field (see the summary).
Although it is conceded that the combination of D2 and Dl does not bring the skilled person directly to the subject- matter of the Claim, the Board is of the opinion, as explained under 4.3, 4.4 and 4.5 above, that the remaining features specified in the Claim are obvious to the skilled person.
4.8. Therefore the Board has come to the conclusion that the subject-matter specified in the Claim does not involve an inventive step, contrary to the requirement of Article 52(1) EPC.
5. Regarding the refund of the appeal fee, the Board observes that the Examining Division had indicated in its first Communication that the application as originally filed did not appear to contain anything that could support an allowable claim. The passage of Dl (page 251, left-hand column) in which reference is made to "time division multiplex" had already been cited in the first Communication albeit without explicit mention of this term.
In any case, reimbursement of the appeal fee can only be ordered where the Board deems that the appeal is allowable (Rule 67 EPC).
6. The present decision is based on documents and arguments which have already been considered by the Examining Division (see the first Communication dated 24.01.1985, in particular the last three paragraphs of page 2). Thus the Board sees no reason to remit the case to the first instance.
For these reasons, it is decided that:
The appeal is dismissed.
The requests for reimbursement of the appeal fee and for remittal of the case to the first instance are refused.