|Date of decision:||19 October 1995|
|Case number:||T 0896/94|
|IPC Class:||G06F 7/50|
|Language of proceedings:||EN|
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|Title of application:||A high performance parallel binary byte adder|
|Applicant name:||International Business Machines Corporation|
|Relevant legal provisions:||
Summary of Facts and Submissions
I. A Partial Search Report was issued on European patent application No. 88 109 439.5 on 4 February 1990, informing the Applicant of a finding of lack of unity of invention. Two groups of inventions were identified, that of claims 1 and 2 being described as "a method of processing a particular byte of two multibyte operands", and that of claims 3 to 10 as an "arithmetic unit for processing an A and a B operand with means of modifying the B operand prior to further processing". No response was made to the invitation to pay an additional search fee and the final European Search Report was issued on 29. May 1991 for the first claimed invention only.
II. In a first communication dated 14 April 1993 the primary examiner supported the lack of unity objection and suggested that it could be overcome by combining the features of claims 3 and 4, by implication in a new independent claim. Claim 4, dependent on claim 3, consisted essentially of the features of claim 1. Further objections were raised, including an objection of lack of clarity in claim 1 because of the absence of essential features.
III. The Applicant submitted a new set of claims including independent claims based on the combination of original claims 3 and 4. The objection under Article 84 EPC that essential features were missing was maintained against these independent claims and, although the Applicant submitted a further amended set of claims, the application was refused on this ground in a decision dated 1 July 1994.
IV. On 28 July 1994 the Appellant lodged an appeal against this decision and paid the appeal fee. On 24 October 1994 a statement setting out the grounds for appeal was filed, together with a set of claims further amended in an attempt to address the ground for refusal.
V. In a communication dated 8 February 1995, the Rapporteur drew the Appellant's attention to Decision G2/92, OJ EPO 1993, 591, in which the Enlarged Board had held that subject-matter for which no search fee had been paid could only be pursued in a divisional application. The preliminary view was taken that regardless of whether or not the claims satisfied Article 84 EPC, they could not be pursued in the application in suit since subject- matter was claimed which had not been searched.
VI. The Appellant thereupon submitted a further new set of claims and stated that these claims were based only on the searched material; since the objection raised by the Rapporteur was new and not related to the original ground for refusal, the case should be remitted to the examining division to decide on this issue, so as to preserve two instances. Decision G10/93, OJ EPO 1995, 172, was cited.
VII. Independent claim 1 of the only request reads as follows:
"A method of processing, in an adder circuit (20), a particular byte of a multibyte A-operand and a multibyte B-operand to produce a processed result, said method comprising the steps of:
performing (20a) the Boolean expression:
m = (b x 8) - 1
where b corresponds to the enumeration of bytes:
Ji-1 = Mi-1T(i+1,m)(Tm+1+SETb)
Ki-1 = Mi-1G*(i,m) + Hi-1(T(i+1,m)(Tm+1+SETb))'G*(i,m)'
Yi-1 = Hi-1G*(i,m)' and
Ei-1 = Mi-1(G*(i,m) + Ti'MASKb)
V = exclusive OR
B' = the one's complement of B
SUMi-1 = the SUM at bit position i-1
T(i,m) = TiTi+1Ti+2 ... Tm-1Tm
Ti = Ai + Bi
Gi = AiBi
Hi = AiVBi
Mi = HiVTi+1
Ai is the ith bit of the A-operand and Bi is the ith bit of the B-operand,
i is an integer,
0. is the most significant bit position and n is the least significant bit position of the result,
Bit position i of the result is less significant than bit position i-1 and more significant than bit i+1 performing (20b) the Boolean expression:
S(m+1,z) = MASKb'G*(m+1,z)+MASKb'T(m+2,z+1)S(z+1,k)+SETb operating on a first subset of consecutive bits of a particular byte of the A-operand and the B-operand yielding a first result:
SUMi-1 = (Ji-1 + Ki-1)S(m+1,z) + (Yi-1 + Ei-1)S(m+1,z)' representing the sum of the first six bits (0-5) associated with the respective bytes of A-operand and B- operand,
operating on at least one further subset of consecutive bits of a particular byte of the A-operand and B-operand yielding at least one further result:
representing the sum of bit 6 associated with the respective bytes of A-operand and B-operand, concatenating (20c), said first result and said at least one further result together thereby producing said processed result without any carry-in effect or carry- out effect on adjacent bits not included in the particular byte of the multibyte operands."
Independent Claim 7 reads as follows:
"An arithmetic unit for carrying out the method according to anyone of the preceding claims."
VIII. The application currently consists of the following documents:
Claims: 1 to 7 submitted on 20 July 1995;
Description: pages 1, 2 and 4 to 65 as originally submitted; pages 3, 3a and 66 received on 13. October 1993;
Drawings: sheets 1 to 11 as originally submitted.
IX. The Appellant requests that the application be remitted to the Examining Division.
Reasons for the Decision
1. The appeal is admissible.
2. G2/92 had not been decided at the time of the first communication from the primary examiner; it was however published in the Official Journal of the EPO in October 1993, some time before the application was refused. The primary examiner's suggestion that a claim based on a combination of original claims 3 and 4 be submitted can be seen to have led the Appellant to the mistaken belief that the original finding of lack of unity of invention, and the subsequent failure to respond to the invitation to pay an extra examination fee, would thereby be overcome. It is unfortunate that neither the Appellant nor the examining division appreciated the implications of G2/92 for the present case, namely that since the subject matter of original claim 3, including for example the feature "modifying the B-operand", had been explicitly excluded from the partial search it was only possible to pursue a claim based on a combination of original claims 3 and 4 in a divisional application.
3. The Appellant has now submitted a set of claims significantly different from those refused, the amendments having been made in response to the Rapporteur's observations. It is therefore appropriate to allow the request that the case be remitted to the Examining Division for further prosecution, so that the Appellant may have the benefit of two instances.
4. It is emphasised that the Board has not considered the allowability of the present set of claims with respect to the requirements of the European Patent Convention.
For these reasons it is decided that:
The application is remitted to the Examining Division for further prosecution on the basis of the present claims (see point VIII. above).