T 0486/89 15-11-1990

1. The appeal complies with Articles 106 to 108 and Rule 64 EPC and is, therefore, admissible.

2. Documents R8 to R11 were filed after expiry of the 9-month period specified in Article 99(1) EPC. The Opposition Division exercised discretion under Article 114(2) EPC to disregard R10 and R11. However, both parties have presented to the Board arguments referring to R8 and R10. The Board has found R10 helpful in throwing light on the prior art chip SAA7010, the details of which are in dispute, and therefore chooses not to disregard it. Since neither party referred to R11 in the present appeal, the Board will not consider it in the reasons for the decision.

3. After hearing the parties, the Board is of the opinion that the closest prior art is the demodulation circuit shown in the upper diagram of Fig. 6 on page 135 of R8. That circuit includes the SAA7010 chip, further details of which are given in R10. Although it does not follow from the Appellant's reference to the decision in case T 56/87 (see IX above), because the circumstances there were different from those in the present case, the Board nevertheless takes the view that a person skilled in the art would read these two references together as relating to the same piece of prior art.

3.1. R8 and R10 disclose a prior art circuit comprising the following features of relevance to Claim 1 of the opposed patent as granted:

A phase locked loop (PLL) control circuit for a digital audio disc (DAD) system, which PLL control circuit includes an oscillator (8.64 MHz VCO) to produce an oscillation signal the frequency of which is controlled by an oscillation control signal, a phase comparator (in the phase and frequency detector block) connected to receive a first electrical signal corresponding to a phase state of a digital audio signal read out from a recording medium of the DAD system and which has inverting period values in a range determined by minimum and maximum period values (Tmin and Tmax) inherently defined in accordance with a chosen modulation technique (EFM), and the oscillation signal from the VCO, respectively, at first and second input terminals for producing a second electrical signal (PD1, PD2) which corresponds to the phase difference between the first signal and the oscillation signal and which is used to control the frequency of the oscillation signal (see connections from PD1, PD2 via the loop amplifier and varicap to VCO1, VCO2, as shown in Fig. 6 of R8), detector means for extracting specific inverting period values (Tmin and Tmax, see R10, page 12, fourth paragraph) from the read-out digital audio signal to provide frequency limit signals for a frequency detector (in the phase and frequency detector block), wherein the frequency detector provides a coarse control signal for the PLL system (see R10, page 12, third paragraph) by generating a third electrical signal (the three state push-pull output FD, see R10, page 4, for pin 23) corresponding to a detected deviation, and adder means (circuitry connected between FD, PD2, PD1, OA1 and OA2) connected to the output terminals of the phase comparator and the frequency detector for adding the second and third electrical signals and for supplying the added signals as said oscillation control signal to the VCO.

3.2. It is appropriate to note here that, in the opinion of the Board, the wording in the characterising part of Claim 1 of the patent as granted, namely "to detect a deviation ... and for generating a third electrical signal corresponding to said deviation", encompasses the possibility that the third signal could be a three state push-pull signal corresponding to the detected presence and direction of a deviation or to the absence of a deviation. The claim does not require a full correspondence with the magnitude of the deviation.

3.3. Thus R8 and R10 explicitly disclose nearly all the features specified in Claim 1 of the opposed patent as granted. The only feature specified in that claim which is not explicitly disclosed in R8 and R10 is the detection of a deviation between the specific inverting period (in practice Tmax) and a period value obtained on the basis of said oscillation signal.

4. The Appellant argued that to a person skilled in the art it was implicit that there must be feedback from the VCO to the frequency detector in the prior art circuit known from R8 and R10, otherwise the PLL loop would be unstable: any deviation detected by the frequency detector would lead to the VCO being controlled to its maximum or minimum frequency, according as the three state push-pull signal FD indicated the frequency of the VCO to be too low or too high. To a person skilled in the art it was, therefore, implicit that the frequency detector in the prior art circuit known from R8 and R10 detected deviation between the specific inverting periods Tmin and Tmax of the EFM signal and corresponding period values obtained on the basis of said oscillation signal.

4.1. The Respondent contested the implication in point 4 above and argued that a direct feedback from the VCO was neither disclosed nor necessary in the system known from R8 and R10. In the motor control system known from R4, Tmax was compared with a constant reference (19, Fig. 3), this being possible because the desired value of Tmax was known beforehand. It must be assumed that in the system known from R8 and R10, as in the present invention (see Fig. 2 of the opposed patent), the clock output of the PLL loop was also used to control the disc drive motor and would consequently affect Tmin and Tmax of the read-out EFM signal.

4.2. The Board notes that the Respondent's assumption that in the system known from R8 and R10 the clock output of the PLL loop was also used to control the disc drive motor is confirmed by R8, see Fig. 5 on page 134, noting the output shown from the SAA7020 chip to the motor control and the corresponding description in the third paragraph of the second column on page 136, according to which any discrepancy between the clock derived in the demodulator (i.e. from the VCO in the SAA7010 chip) and that from the crystal oscillator (in the SAA7020 chip) generates an error signal MCES which controls the speed of the motor spinning the disc.

4.3. Furthermore, it is noted that in the third paragraph on page 12 of R10, which discloses that a frequency detector and a phase detector provide the coarse and fine control signal for the phase locked loop (PLL) system, it is stated that the clock signal (VCO output divided by 2) completes the PLL loop when it is compared with the incoming data in the phase detector. This might be taken to imply that the PLL loop is complete without feedback from the VCO to the frequency detector.

4.4. On the other hand, near the top of page 1 of R10 it is stated: "A nominal 4.3MHz clock locked to the disc rate is also produced." The first item in the list of "Features" is: "Phase locked loop clock regenerator with frequency detector for locking". This might be taken to imply that there is feedback from the VCO to the frequency detector, especially as it belongs to the general knowledge of the person skilled in the art of phaselock circuits that a frequency difference discriminator can be added to a phaselock loop to bring the frequency of a VCO close to that of the signal to which it is to be phaselocked, see the text book R9, section headed Discriminator-Aided Frequency Acquisition, noting that Fig. 5.12 on page 85 of R9 shows a PLL circuit with feedback from a VCO to a phase detector and a frequency difference detector whose outputs (after filtering) are added to produce the control signal for the VCO.

4.5. In the light of the above conflicting considerations, the Board cannot be absolutely sure as to whether the prior art circuit known from R8 and R10 includes feedback from the VCO to the frequency detector or not. The Board resolves this uncertainty to the benefit of the Respondent.

4.6. Such feedback is a requirement of Claim 1 of the patent as granted, which recites "a period value obtained on the basis of said oscillation signal". In the opinion of the Board, this excludes a fixed reference value calculated on the basis of the theoretical value of the frequency of the VCO. In Claim 1 of the auxiliary request, it is explicitly recited that the VCO has an output terminal connected to the detector means (122).

4.7. The Board, therefore, concludes that it has not been proven that Claim 1 of the patent as granted lacks novelty compared with the prior art known from R8 and R10. The same applies to Claim 1 of the auxiliary request.

5. However, as far as the question of inventive step is concerned, the problem solved by the circuit presently claimed according to the main and auxiliary requests, is the provision of a large enough capture range for the PLL. In the opinion of the Board, this problem is an obvious one to want to solve.

5.1. Now, as noted under point 4.4 above, it was already known from R8 and R10 to provide the PLL with a frequency detector for locking, see e.g. the first "Feature" specified on page 1 of R10, although the precise details of how this was done are not clear from R8 and R10. Furthermore, as explained under point 4.4 above with reference to R9, it is part of the general knowledge of the person skilled in the art that one way of implementing the phase locked loop clock regenerator with frequency detector for locking, would be to provide feedback from the VCO to the frequency detector.

5.2. Moreover, as is explained in the right-hand column on page 133 of R8, the EFM signal contains minimum and maximum inverting periods (Tmin and Tmax in the terminology used in the opposed patent) for the express purpose of ensuring that the bit clock can be regenerated.

5.3. It therefore appears to the Board that it would be obvious to a person skilled in the art, starting from the prior art known from R8 and R10 and seeking to fill in the unclear details of the frequency lock on the basis of his general knowledge, to arrange for the frequency detector to detect a deviation between the value of Tmax (and/or Tmin, it doesn't matter) extracted from the read-out EFM signal and a period value obtained from the output of the VCO. In so doing he would make a circuit falling within the scope of Claim 1 of the Respondent's main and auxiliary requests.

5.4. In the result, the Board decides that the subject-matter claimed in Claim 1 of the Respondent's main and auxiliary requests does not involve an inventive step within the meaning of Article 56 EPC. Therefore, the patent cannot be maintained.