T 1110/05 07-10-2008

1. The appeal is admissible.

2. Main request: clarity (Article 84 EPC 1973)

2.1 According to Article 84 EPC 1973, "[t]he claims shall define the matter for which protection is sought. They shall be clear and concise and be supported by the description." Furthermore, according to the opinion G 1/04 of the Enlarged Board of Appeal (OJ EPO 2006, 334, see Reasons 6.2), Article 84 EPC 1973 "signifies that an independent claim within the meaning of Rule 29 EPC [1973] should explicitly specify all of the essential features needed to define the invention, and that the meaning of these features should be clear for the person skilled in the art from the wording of the claim alone." According to established case law, all features which are necessary for solving the technical problem with which the application is concerned have to be regarded as essential features (see Case Law of the Boards of Appeal of the European Patent Office, 5th edition 2006, II.B.1.1.3).

2.2 The application relates to the calculation of the discrete cosine transform (DCT) of a block of pixels. In particular, the application is concerned with the technical problem of calculating in parallel the DCT on several blocks using a hardware architecture which provides for the scalability of the size of the blocks (see paragraphs [0008] to [0010] of the published application).

2.3 Hence method claim 1 should explicitly specify the configuration steps which configure the hardware computational resources and allow calculating in parallel the DCT on several blocks of a given size, the given size being scalable and thus having different values.

2.4 However claim 1 does not explicitly specify such features for the following reasons.

2.4.1 Claim 1 does not explicitly specify in structural terms the hardware computational resources which are used and how they are reconfigured.

2.4.2 The final feature "by reconfiguring the computational resources according to a programmable choice" in claim 1 implies that the hardware computational resources are programmable and allow a choice to be made. Claim 1 also specifies that the hardware computational resources can be used for two different types of calculations. The first type is the calculation of the bidimensional DCT on a block of size N*N and the second type is the simultaneous calculation in parallel of the bidimensional DCTs on all 2**(i)*2**(i) subdivision blocks of the N*N block, i being an integer number. The input values for both types of calculations are the N*N pixel values. But the output values of the different calculations are different and depend on the value of i (disregarding the degenerate case of i = 0). This implies that the hardware must be "configured" or "programmed" in a general meaning to perform the calculation according to the choice made from the different possible calculations. But these implications do not specify which steps are needed to reconfigure the used computational resources.

2.4.3 The remaining features in claim 1 do not specify the method of calculating the bidimensional DCT itself, but instead relate to aspects of fractal image coding. Features of this kind are the attribution of the names "range blocks" and "domain blocks" and the feature that each domain block is superimposable on another domain block by step shifts each of N/2**(i) pixels. These features relate to the generation of pixel blocks which are input to the computational resources but are not features in accordance with point 2.3 above.

2.5 In view of the above, the board judges that claim 1 of the main request is not clear (Article 84 EPC 1973).

3. First auxiliary request: clarity (Article 84 EPC 1973)

3.1 Claim 1 of the first auxiliary request differs from claim 1 of the main request essentially in that it comprises the following two features

- "attributing a different value of a size selection variable, referred to as size, for said maximum or domain block size N*N and for the selectable different sizes N/2**(i)*N/2**(i) of said range blocks" and

- "programmably selecting a value of said variable size for modifying the configuration of said hardware DCT computing resources for producing said N*N DCT coefficient values".

3.2 The configuration or programming of the hardware computational resources discussed in the context of the main request (see point 2.4.2 above) requires distinguishing the different block sizes (and thus the corresponding different calculations). Thus the two above features of claim 1 of the first auxiliary request have the technical meaning that the hardware computational resources are such that they can be "configured" or "programmed" by selecting a value of a size selection variable which distinguishes the different selectable block sizes. Since the claim does not specify any configuration or calculation steps which are dependent on the variable, these features do not specify the method steps more precisely than the features of claim 1 of the main request. In particular, the claim does not specify which steps are needed to reconfigure the computational resources for the calculation of the different size blocks using the same hardware computing resources. Thus the objection as to lack of clarity raised against claim 1 of the main request is also valid against claim 1 of the first auxiliary request.

3.3 Hence the board judges that claim 1 of the first auxiliary request is not clear (Article 84 EPC 1973).

4. Second auxiliary request

4.1 Claim 1 of the second auxiliary request differs from claim 1 of the first auxiliary request essentially in that it comprises the features a) to e) (see point VII above). These features specify that range blocks of a certain size are ordered, 2**(i) monodimensional DCTs are calculated in parallel and the output sequences of the monodimensional DCTs are processed to complete the calculation of the 2**(i) bidimensional DCTs. Hence the hardware computational resources have a two-stage functionality of calculating in a first stage a number of monodimensional DCTs depending on the value of the size selection variable and in a second stage the bidimensional DCTs based on the output of the first stage.

4.2 The application explains in detail the mathematical considerations which result in the conclusion that the 4*4 and the 8*8 bidimensional DCTs can be calculated by first calculating monodimensional DCTs and then calculating the bidimensional DCT starting from the monodimensional DCTs (see paragraphs [0050] and [0069]). This partition of the calculation in two stages also allows the calculation of four 4*4 DCTs in parallel (see paragraphs [0057] to [0062], [0083] to [0093] and figure 12).

4.3 Hence the size-dependent two-stage functionality of the hardware computational resources reflects the finding that certain bidimensional DCTs can be calculated in two stages as discussed in point 4.2 above. And since the partition in two stages also allows calculating certain DCTs in parallel, the two-stage functionality of the hardware computational resources is also one of the features which is described as solving the problem underlying the invention (see point 2.3 above).

4.4 Hence the argumentation developed in section 2.4 above is not valid for the second auxiliary request.

5. Remittal (Article 111(1) EPC 1973)

5.1 The reasons concerning Article 56 EPC 1973 given in the decision under appeal do not apply to the subject-matter of claim 1 of the second auxiliary request. For claim 1 of the second auxiliary request comprises not only the "important features of the disclosure" considered in the decision under appeal, but also essential features (see points 3.1 and 4.1 above) which are not discussed in the decision under appeal.

The board notes that the reasons given in the decision under appeal only concern claim 1. Nothing can be derived from the decision under appeal concerning the subject-matter of original claim 2, which is now in essence included in claim 1 of the second auxiliary request.

5.2 The other objections raised in the decision under appeal (see point II above) relate to features which are not present in claim 1 of the second auxiliary request ("least acceptable alternative request" as it is headed). No additional reasons are given in the decision under appeal for the statement that "[t]he examining division sees no patentable matter in the application". The examining division will have to examine whether claim 1 sets out in a sufficiently clear manner the size-dependent two-stage functionality which seems to find support in the description (see paragraphs 4.2 and 4.3 above) and whether it defines patentable subject-matter.

5.3 Hence the board judges the appeal to be allowable on the basis of the second auxiliary request.

5.4 It follows from points 5.1 and 5.2 that the amendments made in appeal proceedings require further substantive examination. Furthermore the amendments comprise apparent deficiencies such as an incomplete claim 2 of the second auxiliary request and references to "2i" DCTs and vectors in claim 3 of the second auxiliary request whereas claim 1 refers to 2**(i) DCTs or vectors.

5.5 In view of the above, the board has decided to remit the case to the first instance in application of Article 111(1) EPC 1973.

6. Reimbursement of the appeal fee (Rule 67 EPC 1973)

6.1 Rule 67 EPC 1973 applies for the reasons given in decision J 10/07 (to be published in the Official Journal), point 7. According to Rule 67 EPC 1973, "[t]he reimbursement of the appeal fee shall be ordered in the event of interlocutory revision or where the Board of Appeal deems an appeal to be allowable, if such reimbursement is equitable by reason of a substantial procedural violation."

6.2 The appellant has raised two distinct criticisms of the procedure before the first instance (see points IV and X above) which concern potential substantial procedural violations.

6.3 Concerning the first criticism (refusing the application on the basis of an allegedly dropped objection), there is no indication in the file that the objection under Article 56 EPC 1973 had been withdrawn or dropped. On the contrary, when issuing the summons to oral proceedings pursuant to Rule 71a(1) EPC 1973 the examining division informed the applicant as follows.

"In view of paragraph 1 above, the added features should be removed from the claims. However in this case, the claims would be the same as those already objected to in the communication of 25. 11. 03 so that the same objections still apply."

6.4 The communication of 25 November 2003 (see page 2, paragraph 2) had raised an objection under Article 56 EPC 1973 based on a combination of D2 and D3. The applicant presented his comments to this objection in a letter dated 6 May 2004. Hence the applicant objectively could expect that this objection could be raised in the oral proceedings before the examining division and could ultimately constitute a reason to refuse the application. Thus the decision under appeal was based on a ground on which the applicant had an opportunity to present his comments (Article 113(1) EPC 1973).

6.5 Concerning the second criticism (lack of reasoned communications), the appellant has substantiated why the reasoning in the communications pursuant to Article 96(2) EPC 1973 concerning lack of inventive step on the basis of D2 and D3 was allegedly insufficient. Lack of inventive step was a ground for refusing the application and was based on the factual reasons derived from D2 and D3 (see point III above).

6.6 The factual reasons concerning claim 1 were set out in the communication dated 25 November 2003 (page 2, paragraphs 1 and 2) as follows.

"In the reply of 2.4.03 it was argued that the subject matter of claim 1 is distinguished from the prior art because the computations are carried out in parallel. However parallel computation is a well-known technique for speeding up calculations and it would be obvious for the skilled person to use this technique here as well. Furthermore, if is not obvious exactly how to implement the parallel computations, then the features which make this possible should be included in the claim, otherwise the claim is missing essential features (Article 84 EPC).

A VLSI chip is known from D3 which can carry out computations on several different sized blocks (see "chip features", page 701). As is clear from "operative part" on page 703, the chip may calculate DCTs in parallel. It would therefore be obvious for the skilled person to use such a chip with e.g. the method disclosed in D2 and thus arrive at the subject-matter of claim 1. Claim 1 is therefore not allowable."

6.7 The applicant had indeed emphasised in the reply of 2 April 2003 the feature that the computations were carried out in parallel. The board sees nothing wrong in limiting the above analysis of D3 to the emphasised feature. Moreover the objection contained a refutable reason (the chip of D3 was able to calculate DCTs in parallel) why a person skilled in the art would have combined the teachings of D2 and D3. Thus the argumentation was brief but intelligible and gave the applicant an opportunity to provide his comments such as those submitted in the statement of grounds of appeal.

6.8 The question whether the above analysis of D3 is correct is a question of assessment of prior art. If the analysis is incorrect, this has to be regarded as a substantive error, not a procedural violation. Thus the merits of the above analysis need not be considered in the given context.

6.9 The first instance's reasoning in the communications pursuant to Article 96(2) EPC 1973 concerning other objections did not have a substantive effect on the outcome of the proceedings and therefore could not at any rate amount to a procedural violation that could be considered to be substantial.

6.10 In view of the above the board judges that no substantial procedural violation has occurred. Thus the request for reimbursement of the appeal fee must be refused.