T 0724/10 (Synchronous DRAM device/RAMBUS) 07-10-2015

I. The patent proprietor (hereinafter: the appellant) appeals the opposition division's decision, dated 8 March 2010, to revoke European patent No. EP 1 197 830.

II. The patent originates from European patent application EP02000378.6, a divisional of the earlier application EP99118308.8 (the "parent application"). The parent application is, in turn, a divisional application originating from the application EP919083741.1 (the "root application"), published as WO 91/16680 A1.

III. The opposition division revoked the patent on the ground that the subject-matter of "all requests" extended beyond the content of the root application as filed (Article 100(c) EPC).

IV. The requests at the start of the oral proceedings lasting two days (from 8 to 9 December 2009) were a main request and four auxiliary requests (I to IV) filed with letter dated 5 November 2009.

V. On the first day of oral proceedings , the proprietor filed amended auxiliary requests I and II; the previous auxiliary requests I to IV were maintained and renumbered as auxiliary requests III to VI.

VI. On the second day of the oral proceedings, the proprietor submitted a new version of auxiliary request I, replacing both auxiliary requests I and II filed the day before. The other auxiliary request were again renumbered, this time as auxiliary requests II to V. At the end of the oral proceedings, the requests were, thus, as follows:

- the main request of 5 November 2009;

- auxiliary request I of 9 December 2009;

- auxiliary requests II to V corresponding to

auxiliary requests I to IV of 5 November 2009.

VII. The appellant requested that the decision under appeal be set aside and that the patent be maintained on the basis of the main request of 5 November 2009 or one of the following auxiliary requests:

auxiliary request I of 9 December 2009;

auxiliary requests II to III of 5 November 2009;

auxiliary request IV to VII as filed with the statement setting out the grounds of appeal.

The appellant also requested the reimbursement of the appeal fee on the ground of a substantial procedural violation (Rule 103(1)(a) EPC), and oral proceedings as an auxiliary request.

The appellant's arguments, in so far they are relevant to the present decision, can be summarized as follows:

In its decision, the opposition division did not give reasons why auxiliary request I, as filed on the second day of the oral proceedings, contravened Article 100(c) EPC. Instead, the decision dealt with the withdrawn auxiliary requests I and II, filed on the first day of the oral proceedings. Ignoring the proprietor's amended requests was a substantial procedural violation according to T 543/92 and T 89/94.

VIII. Opponent I replied that it had nothing to add beyond the arguments made during the first instance procedure. It subsequently withdrew its opposition to the patent.

Opponent II responded to the statement of grounds that, while it was apparent that the written decision dealt with the wrong version of auxiliary requests I and II, the proprietor was not adversely affected. All requests were extensively discussed during the oral proceedings, and it was clear that they all had the same problem in the "opcode" feature.

Opponent II has also withdrawn its opposition to the patent.

IX. Claim 1 of the main request reads:

"A synchronous Dynamic Random Access Memory (DRAM) semiconductor device including a memory array having a plurality of dynamic memory cells, wherein the memory device comprises:

connection means adapted to connect the DRAM to an external bus which is a part of a semiconductor bus architecture, the semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to the external bus, wherein the external bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by the DRAM for communication with substantially every other semiconductor device connected to the external bus, the connection means being adapted to receive multiplexed addresses;

clock receiver circuitry to receive an external clock signal;

a programmable access-time register for storing a value which is representative of a number of clock cycles of the external clock signal (53, 54) to transpire after which the DRAM responds to an operation code, the programmable access-time register being accessible to the external bus through the connection means, wherein to set the value in the programmable access-time register data is transmitted to the programmable access-time register over the external bus;

sense amplifiers, coupled to the memory array, to sense data from the dynamic memory cells;

a plurality of input receivers to sample the operation code synchronously with respect to a first transition of the external clock signal, wherein the operation code instructs the memory device to:

perform a read operation such that the memory device outputs the data sensed by the sense amplifiers; and

precharge the sense amplifiers automatically after the data is sensed;

and

a plurality of output drivers (76) for outputting the data onto the external bus (18, 65) in response to the operation code, wherein the output drivers (76) output the data on the external bus (18, 65) after the number of clock cycles of the external clock signal transpire and synchronously with respect to the external clock signal (53, 54), so that receipt of the operation code and the corresponding response are separated by the number of clock cycles as selected by the value stored in the programmable access-time register, wherein each output driver of the plurality of output drivers (76) outputs the data onto the external bus (18, 65) at a bus cycle data rate that is twice the rate of the external clock signal."

X. According to a handwritten annex to the minutes of oral proceedings, auxiliary request I, as filed on the first day of the oral proceedings, included the following text:

"wherein, when the operation code is part of a request packet consisting of a contiguous series of bytes, the access time is also representative of a time between receipt of the request packet and the corresponding response."

XI. Claim 1 of auxiliary request I, as filed on the second day of the oral proceedings, differs from claim 1 of the main request by the addition of the following feature after the word "access-time register" at the third line from the end:

"wherein the value stored in the register is also representative of an amount of time between receipt of all information required to enable the DRAM to respond to the operation code and the corresponding response,"

XII. Auxiliary request II filed as on the first day of the oral proceedings includes the following text:

"wherein, when the operation code is part of a request packet consisting of a contiguous series of bytes, the value stored in the register is also representative of a time between receipt of the request packet and the corresponding response,

wherein, when the operation code is not part a request packet, the value stored in the register is also representative of a time between receipt of all information required to enable the memory device to respond to the operation code and the corresponding response."