T 0904/01 23-10-2001

I. European patent application No. 96 101 521.1 (publication No. 0 725 447) was refused by the decision of the examining division, dispatched on 12 March 2001.

The reason for the refusal was that the subject-matter of apparatus claim 1 according to applicant's main request and the corresponding method claim 6 lacked an inventive step in the meaning of Article 56 EPC in view of the combined teachings of the documents:

D1: Patent Abstracts of Japan Vol. 17, No. 178 (E-1347), 7 April 1993 & JP-A-04332178.

D2: Hewlett-Packard Journal, Vol. 40, No. 5, 1 October 1989, pages 69 to 75.

As to the further claims the examining division referred to its communication dated 28 April 1997, in which it had expressed its view that the subject-matter of apparatus claim 4 (erroneously referred to as "claim 9") and of the corresponding method claim 9 did not appear to involve an inventive step having regard to documents:

D3: Journal of Crystal Growth, Vol. 107, No. 1/4, 1. January 1991, pages 855 to 859

D4: IEEE Photonics Technology Letters, Vol. 2, No. 7, July 1990, pages 505 to 506,

and that the dependent claims 2, 3, 5, 7, 8 and 10 did not appear to contain any additional features which, in combination with the features of any claim to which they referred, involved an inventive step.

With respect to claim 1 according to the auxiliary request the examining division was of the opinion that this claim was not admissible under Article 123(2) EPC.

II. The applicant lodged an appeal against this decision. The notice of appeal was received on 22 May 2001, the prescribed fee being paid on the same day. The statement setting out the grounds of appeal was received on 12 July 2001.

III. With the statement of grounds of appeal, the appellant submitted a new set of claims 1 to 9 to replace those previously on file. The wording of independent claim 1 is:

"A pin type light receiving device (1, Fig. 4), comprising:

a) a semiconductor substrate (InP+Fe; 20) made of InP;

b) a first semiconductor layer (30; n-type InP) formed on said semiconductor substrate (20) and doped with an impurity (Si) of a first conduction type (n);

c) a second semiconductor layer (31) formed in a mesa shape on said first semiconductor layer (30) and made of a first semiconductor material (n- type GaInAs, i-type) without intentionally doping said first semiconductor material with an impurity (i-type);

d) a third semiconductor layer (32) formed in a mesa shape on said second semiconductor layer (31) and made of said first semiconductor material (GaInAs) doped with an impurity (Zn) of a second conduction type (P) different from said first conduction type (n);

e) a second electrode layer (61) formed in ohmic contact on said third semiconductor layer (32); and

f) a fourth layer (40) formed around said first to third layers (30, 31, 32);

g) an insulator layer (80) formed around said semiconductor substrate and said first to fourth layers;

h) a first electrode layer (60) formed in ohmic contact on said first semiconductor layer (30);

i1) said fourth layer (40) being made of a second material (InP); and

i2) said second material (InP) having a band gap energy greater than that of said first semiconductor material commonly used in said third and second layers (32, 31);

characterized in that

i1') said second material (InP), of which said fourth layer (40) is being made, is a second semiconductor material (InP); and

i1'') said second semiconductor material (InP) is unintentionally doped with an impurity (i-type); and

j) an impurity diffusing region (33) is formed (Fig. 4) in the interfacial regions of the fourth semiconductor layer (40; i-type InP) and the second semiconductor layer (31; n- type GaInAs; i-type) in contact with the third semiconductor layer (32; p-type (Zn doped) GaInAs) by diffusing the impurity (Zn) of the second conduction type (P) from the third semiconductor layer (32; p-type (Zn doped) GaInAs) into the interfacial regions of the fourth semiconductor layer (40; i-type InP) and the second semiconductor layer (31; n- type GaInAs; i-type) in contact with the third semiconductor layer (32; p-type (Zn doped) GaInAs) to dope the interfacial regions therewith."

The wording (including several typographical errors) of independent claim 6 is:

"A fabrication process of pin type light-receiving device, comprising:

a first phase of successively laminating a first semiconductor layer (30; n-type InP) doped with an impurity (3i) of a first conduction type (n), a second semiconductor layer (31) made of a first semiconductor material (n-type GaInAs, i-type) with intentionally doping said first semiconductor material with an impurity (i-type), and a third semiconductor layer (32) made of said first semiconductor material (GaJuAs) doped with an impurity (Zn) of a second conduction type (8) different from said first conduction type (n) on a semiconductor substrate (20);

a second phase of removing peripheral regions of said second and third semiconductor layers (31, 32) formed in said first phase, thereby processing said second and third semiconductor layers (31, 32) each in a mesa shape;

a third phase of forming a fourth semiconductor layer (40) made of a second semiconductor material (InP) having a band gap energy greater than that of said first semiconductor material (GaJuAs) without intentionally doping the second semiconductor material (InP) with an impurity, around said second and third semiconductor layers (31, 32) processed in the mesa shape in said second phase and around said first semiconductor layer (30);

a fourth phase of removing predetermined regions of said fourth semiconductor layer (40) formed in said third phase so as to expose predetermined regions of said first and third semiconductor layers (30, 32), then forming a first electrode layer (60) in ohmic contact on said first semiconductor layer (30), and forming a second electrode layer (61) in ohmic contact on said third semiconductor layer (30, 31); and

said third phase comprises a heating treatment for diffusing the impurity (Zn) of said second conduction type (P) from said third semiconductor layer (32) into an interfacial region of said fourth semiconductor layer (40) in contact with said third semiconductor layer (832), thereby doping the interfacial region with the impurity."

IV. As his main request the appellant requested to transfer the case back to the examining division for further examination of the application on the basis of the new claims. On an auxiliary basis the appellant requested reversal of the decision under appeal and grant of a patent on the basis of the new claims, or the scheduling of oral proceedings, if a patent could not be granted in written proceedings.

In support of the main request, the appellant argued substantially as follows:

The new claim 1 is essentially based on a combination of claim 1 of the main request of the decision under appeal and claim 2 as originally filed and furthermore contains a feature j) based on the passages on page 32, first paragraph; page 10, second paragraph; and page 31, lines 10 to 22 of the application as filed. Method claim 6 is supported by the same passages from the description and by original claim 7. With respect to the features defined in claims 2 and 7 as originally filed the examining division had only made a rather general statement in the communication of 28 April 1997. Neither this statement nor the decision under appeal included any explicit reasons as to why the subject matter of these claims did not involve an inventive step. This subject-matter refers to an additional diffusion region 33 according to the embodiment of Fig. 4 providing a further reduction of the leak current flowing along the wall surfaces, which is the problem addressed in the patent application. Neither documents D1 and D2, nor the further prior art documents disclose or suggest to further reduce the leak current in this way. However, since the examination by the first instance did not include these aspects on which the new independent claims are based, the case should be remitted for further examination.