T 0486/07 (Processing intersymbol interference with RSSE/LUCENT) 26-11-2010

1. Admissibility

The appeal complies with the provisions of Articles 106 to 108 EPC 1973, which are applicable according to J 0010/07, point 1 (see Facts and Submissions, point II above). Therefore the appeal is admissible.

2. Non-attendance at oral proceedings

In its letter of 25 November 2010 the appellant announced that it would not be represented at the oral proceedings. The board considered it expedient to maintain the date set for oral proceedings. Nobody attended the hearing on behalf of the appellant.

Article 15(3) RPBA stipulates that the board shall not be obliged to delay any step in the proceedings, including its decision, by reason only of the absence at the oral proceedings of any party duly summoned who may then be treated as relying only on its written case.

Thus, the board was in a position to take a decision at the end of the hearing.

Main request

3. Article 84 EPC

3.1 Independent method claim 1 specifies a sequence of steps which is not supported by the description. Claim 1 leaves open whether the step of using reduced state sequence estimation (RSSE) takes place before the step of using an algorithm of lower complexity (e.g. decision feedback equalizer DFE). This is in contrast to original claim 1 and to column 3, lines 5 to 8, ("The DFE technique initially removes the intersymbol interference associated with the tail taps, then the RSSE technique is applied only to the more important tail taps" - emphasis added) and column 4, line 41 ("Thereafter") or line 44 ("initially") of the application as published. Claim 1 is therefore not supported by the description in this regard.

3.2 In addition, the expression "lower complexity" was objected to in the appealed decision. The appellant argued that the complexity of an algorithm according to claim 1 was based on the number of taps. However, as is apparent from the examining division's argument that the complexity can depend on the number of computations required to carry out the algorithm, the board is not convinced by the appellant's argument that the skilled person would recognise that the claimed invention is directed to the number of taps as the criterion for complexity. In the light of the fact that the application explicitly refers to the hardware complexity (see the last sentence of paragraph [0016] of the published application), it is conceivable that the complexity depends on the space for a hardware implementation on a chip and it is at least unclear according to which criterion it is to be decided whether the complexity is "lower", rendering the wording of claim 1 unclear. The appellant's arguments submitted with letter dated 25 October 2010 (see page 2, last paragraph onwards), based on the assumption of a decision feedback unit DFU with parallel decision feedback cells DFC, are not convincing, because the wording of a claim has to be clear in itself without there being a need for the skilled person to refer to the description (see e.g. T 1129/97, OJ EPO 2001, 273). Claim 1, however, in contrast to the specific embodiment of the description referred to by the appellant, does not specify a decision feedback unit DFU with parallel decision feedback cells DFC and therefore does not allow the skilled person to infer according to which criterion it is to be decided whether the complexity is "lower".

Claim 1 therefore does not to fulfil the requirements of Article 84 EPC.

First auxiliary request

4. Article 84 EPC

4.1 In the appealed decision, independent claim 1 was objected to because the expressions "more significant taps" and "less significant taps" were considered to be unclear. The board agrees that there is no established meaning of these expressions in the art.

4.2 According to the appellant's argumentation, an interpretation of the expressions objected to in the light of the description could be based either on the tap value or the tap position. With regard to an interpretation directed to the tap value, the appellant referred to the following passage of the description:

"the initial taps provide the largest contribution to the signal energy of the channel output, and the corresponding power decreases to zero as the taps approach infinity" (see paragraph [0012] of the application as published). However, for referring to a tap value, as argued by the appellant, it remains unclear what exactly is such a "largest" contribution (e.g. 60% or 80% etc.). The disclosure is silent in this regard, leaving the skilled reader in doubt as to how to distinguish between more significant and less significant taps.

4.3 Regarding an interpretation directed to the tap position, the description discloses that

"the less significant tail taps (U+1 through L) are processed with a lower complexity cancellation algorithm, such as a decision-feedback equalizer (DFE) technique, that cancels the tail taps using tentative decisions. Thereafter, only the more significant initial taps (1 through U) are processed with a reduced state sequence estimation (RSSE) technique." (see paragraph [0008] of the application as published).

4.4 The application fails to give any embodiment for a concrete value of U. According to e.g. column 3, line 15, "a well-chosen value of U" is required. According to the last sentence of paragraph [0016] of the published application, the "design parameter U" is a crucial feature for solving the problem of the invention, which, however, is not specified in claim 1. While the board agrees with the appellant's argument that the "predefined percentage of the overall signal energy" is a design choice (see page 2, second paragraph of the letter dated 25 October 2010), claim 1 neither makes reference to the "overall signal energy" nor gives any information regarding the position U being the criterion on which a distinction between more significant taps and less significant taps is to be made.

Therefore, the subject-matter of claim 1 is considered to be an undue generalisation of the "overall signal energy". Claim 1 is therefore not supported by the description in the whole range claimed.

Claim 1 therefore does not fulfil the requirements of Article 84 EPC.

4.5 The expression "lower complexity" is still part of claim 1 and the afore-mentioned problem of lack of clarity therefore persists.

Claim 1 therefore does not fulfil the requirements of Article 84 EPC, for the reasons set out in point 3.2.

Second auxiliary request

5. Article 84 EPC

The expression "lower complexity" is still part of claim 1 and the problem of lack of clarity as presented above therefore persists.

Claim 1 therefore does not fulfil the requirements of Article 84 EPC, for the reasons set out in point 3.2.

Third auxiliary request

6. Article 123(2) EPC

The board has doubts that the application provides for a direct and unambiguous disclosure of the parameter K introduced with the added features of this request, in particular with regard to the relation between the parameters U and K. Paragraph [0015] of the published application refers to an Index "k" for the channel taps fk, followed by a relation K<=U<=L for "K" (i.e. capital K). In the next paragraph it is disclosed that K can be the number of taps that are accounted for in the combined code and channel state inside the RSSE circuitry 500. The exact relation between K and U according to the added feature of claim 1 of this request is, however, ambiguous.

7. Article 84 EPC

The expression "lower complexity" is equally part of claim 1. For the reasons given above (see point 3.2), claim 1 does not fulfil the requirements of Article 84 EPC.

8. Inventive step - Article 56 EPC

Even if the requirements under Articles 84 and 123(2) EPC were fulfilled, the subject-matter of claim 1 of this request at least would not involve an inventive step.

8.1 D1, which is considered to be the closest prior art document, discloses a decision feedback equalizer DFE as a prefilter to a Viterbi Decoder VA, in which the DFE has been embedded to truncate the channel impulse response through feedback subtraction (see figure 2, section II of D1), which is suitable for processing a signal received from a dispersive channel (see e.g. page 971, right-hand column, second paragraph) and which is modelled as a filter having taps (see in particular equations 2 and 3). In the board's view figure 2 of D1 can be compared to figures 2 and 4 of the published application with the exception that figure 2 of D1 shows a Viterbi algorithm VA in contrast to element 500 in figure 2 of the application showing the reduced state sequence estimation (RSSE) circuitry.

8.2 In the decision under appeal it was argued that the feature of a reduced state sequence estimation (RSSE) algorithm of claim 1 could be interpreted in a broad manner. The examining division argued that from the disclosure "the first V out of the total number of v of intersymbol interference terms are to be operated on by the VA ..., resulting in an M**(v)-state receiver" (see the text following equation 2 of D1) it followed that a reduced state sequence estimation (RSSE) was used, since V was smaller than v and the number of trellis states was reduced from M**(v) to M**(v). D1 further disclosed that the remaining intersymbol interference should be equalised with DFE making a tentative decision (which corresponds to the embodiment given in paragraphs [0008] and [0013] of the description of the published application).

8.3 The board agrees with the examining division that the formulation of the feature "a reduced state sequence estimation technique" of claim 1 can be interpreted in a broad manner, since the application does not give a concrete definition of what exactly is to be understood by this expression according to the claimed invention, hence not limiting the scope of this feature. Therefore any technique which cancels intersymbol interference (ISI) contribution taps and which can be regarded as RSSE falls under the scope of claim 1. In principle, the reduced-state sequence estimation is a detection algorithm that provides a direct trade-off between complexity and performance in the presence of intersymbol interference channels by reusing determined data in order to reduce the hardware size (as also disclosed in D1, e.g. page 973, left-hand column, last sentence of second paragraph, or section IV). It employs the basic idea of set partitioning for obtaining reduced state trellises (see for example paragraphs [0005] and [0006] of the published application).

8.4 In the passage "the first V out of the total number of v of intersymbol interference terms are to be operated on by the VA ..., resulting in an M**(v)-state receiver" (see page 972, right-hand column, last paragraph), D1 explicitly discloses that this is done with the "first" intersymbol interference (ISI) terms. According to claim 1 the more significant taps are usually the intial taps or taps 1 to U. By operating with a Viterbi algorithm on the first V of the ISI terms, D1 discloses processing the more significant taps with the reduced state decoder. The "rest" of the ISI terms are equalised by a DFE as a prefilter (see figure 2 of D1), which terms can apparently therefore be regarded as the less significant taps being processed prior to the ISI due to the more significant taps according to claim 1.

8.5 Since DFE is used for equalisation, the board does not agree with the appellant's argument that D1 used the DFE only to reduce the number of states and taught away from the use of DFE to reduce the number of taps (see the paragraph bridging pages 4 and 5 of the statement setting out the grounds of appeal). The subject-matter of claim 1 requires that all L taps are processed either with RSSE or with a cancellation algorithm using tentative decisions such as DFE.

8.6 According to the description of the application as referred to above, under certain circumstances (here DFSE being a specialisation of RSSE for U=K becomes a pure Viterbi decoder) RSSE can result in using a Viterbi algorithm for processing intersymbol interference. The appellant argued that the claims did not cover the case of a DFSE with U=K (see the statement setting out the grounds of appeal, page 3, paragraphs 4 and 5). In particular, the statement "The limitations in the cited claim … do not contradict the statements in the specification that … the present invention includes the case U equal to K" is not clear to the board. Because of the appellant's absence during oral proceedings, this issue could not be clarified. The board still has doubts that this is correct, because the corresponding feature of claim 1 does not exclude the embodiment with U=K as described in the application.

8.7 Even if one assumed that the special case with U=K as disclosed in the present application was not comprised by the subject-matter of claim 1, and one interpreted the feature of a reduced state sequence estimation (RSSE) algorithm in a narrow manner (having a particular meaning as argued by the examining division), it has to be considered that D1 already suggests the idea of reducing the number of intersymbol interference (ISI) terms to be operated on by the Viterbi algorithm (see page 972, equation (2) and subsequent text). D1 explicitly suggests to "simplify the VA itself" (see page 972, left-hand column, fourth paragraph).

The skilled reader of D1 is therefore motivated to take other reduced state techniques into consideration in order to find a solution for the problem of reducing hardware complexity and optimising the critical path of the Viterbi algorithm used in D1, which is considered to be the objective problem underlying the only difference between the subject-matter of claim 1 and the teaching of D1, i.e. the concrete type of algorithm used for reducing the number of trellis states.

8.8 As described in the introductory portion of the present application, RSSE was a technique which was well known before the priority date of the present application. As an example, see the publication D2 which discloses a reduced-state decoding technique similar to the embodiment using DFSE described in paragraph [0024] of the present application (see D2, page 671, left-hand column onwards, in particular the disclosure dealing with the case K

8.9 This is in contrast to the appellant's argument that D2 computed all of the ISI terms using an RSSE technique (see page 4, paragraph 4 of the statement setting out the grounds of appeal), which therefore does not convince. The board interprets D2 to the effect that the ISI terms 0 to K can be considered to correspond to the more significant taps, whereas the remaining K to L ISI terms correspond to the less significant taps. Hence, D2 discloses a reduced-state decoding technique similar to the DFSE of the embodiment described in paragraph [0024] of the present application (see D2, page 671, left-hand column onwards) and further implies the use of DFE for processing ISI terms. D1 discloses placing a DFE in front of the Viterbi decoder. As argued above, the board does not agree with the appellant's argument that D1 used the DFE only to reduce the number of states and taught away from the use of DFE to reduce the number of taps. The subject-matter of claim 1 requires that taps 1 to U are processed with a reduced-state sequence estimation algorithm RSSE and taps U+1 to L are processed with a cancellation algorithm using tentative decisions such as DFE. The board therefore judges that the skilled person would take a combination of the teaching of D1 with that of D2 into consideration without the use of inventive skills, thereby arriving at a solution of the objective problem by using the RSSE technique DFSE instead of the Viterbi decoder disclosed in D1.

8.10 As far as the appellant's argument on page 4, paragraph 4 of the statement setting out the grounds of appeal and on page 8, paragraph 3 of the letter dated 25 October 2010 regarding the allegedly surprising results of the claimed invention is concerned, the board notes that even if the publications mentioned by the appellant contained such a statement, this is merely a secondary consideration showing the subjective opinion of the authors, but not an objective reasoning that an inventive activity was involved. It has to be considered that the author of the publications referred to by the appellant is one of the inventors of the present application. The statements in the cited publications therefore only show that the inventor has overcome his own prejudice which is not considered to be an indication of the existence of an inventive step. In particular, no indication is given that there had been an objective long-felt need for a solution or an objective technical prejudice in the art which could indicate that technical hurdles had to be overcome. This argument of the appellant is therefore not convincing.

Therefore the board concludes that the subject-matter of claim 1 is obvious in the light of a combination of the teachings of publications D1 and D2.

9. Thus, none of the four requests is allowable.