T 0596/94 11-03-1999

1. The appeal is admissible.

2. Article 123(2) EPC

2.1. As compared with claim 1 as originally filed, the amended claim 1 includes the following further features, which are numbered as well as underlined in the wording of the claim:

A semiconductor memory device comprising a silicon substrate (11) and having a memory cell portion and a peripheral circuit portion, the memory cell portion comprising a memory cell array (110, 111) which includes a plurality of memory cells having word lines and memory cell capacitors(1), and having a first insulation film (20) of silicon dioxide(2), with a first contact hole (31) formed in the first insulation film(3) and a first metallization film (40) formed on the first insulation film, the first metallization film including a polysilicon film (21) and a refractory(4) metal silicide film (22) which are stacked in this sequence, the first metallization film constituting at least bit lines of said memory cell portion which are connected to said substrate via said first contact hole (31)(5); characterized in that the device further comprises a second insulation film (17) of silicon dioxide upon which is formed the first insulation film (20)(6), the peripheral circuit portion having a second contact hole (33, 34), the first and second contact holes (31, 33, 34) being formed through the second insulation film (17)(7); in that said first metallization film contacts the silicon substrate (11) through the second contact hole (33,34) so as to further constitute a barrier layer (50, 60) in said peripheral circuit portion(8) which is formed in said second contact hole (33, 34) and around a periphery thereof(9) such that said polysilicon film (21) is in contact with said second insulation film (17)(10); and in that a second metallization film (29, 30) of an alloy of aluminium and silicon overlies the barrier layer (50, 60) in the second contact hole (33, 34) whereby it is in contact with said refractory metal silicide film (22), said second metallization film constituting wiring of said peripheral circuit portion(11).

The amendments (1) to (11) are supported by the original disclosure. In particular:

(1) See claim 2, page 9, lines 7, 8, 22 to 24, page 11, lines 13 to 15, Figure 3B.

(2) See page 9, lines 25, 26.

(3) See page 9, lines 31 to 35.

(4) See claim 4, page 10, lines 21 to 24.

(5) See page 10, lines 5 to 11, Figure 3B. The expression "at least" is justified by the fact that the first metallization film constitutes bit lines 40 as well as barrier layers 50, 60.

(6) See page 8, lines 29 to 32, page 9, lines 25 to 27, Figure 3B.

(7) See page 9, lines 27 to 35, Figures 3A, 3B.

(8) See page 10, lines 5 to 15, Figures 3A, 3B.

(9) See Figures 3A, 4.

(10) See Figure 3A, 4.

(11) See page 11, lines 10 to 15, Figure 3A.

2.2. In the decision under appeal, point II.2, the Examining Division raised an objection under Article 123(2) EPC against amendment (9). This objection is not well founded.

The fact that the Examining Division admitted (see page 4, first paragraph) that Figure 3A shows a barrier layer 50, 60 filling the second contact holes 33, 34 and extending around these holes, indicates, in the Board's judgement, that the amendment is indeed admissible. Notwithstanding the disclosure of Figure 3A, the Examining Division, however, came to the conclusion that feature (9) goes beyond the content of the application as filed in view of the fact that there is not sufficient disclosure in terms of structure and function of this feature which is meant to define an inventive merit over the prior art, in particular as regards the alleged improved adhesion of the barrier layer to the underlying layer. In support of its conclusion, the Examining Division cited decision T 241/88. In this decision the Board emphasised that, in accordance with the earlier decision T 169/83 (OJ EPO 1985, 193), in order for features contained in the drawings to be included in the claims "the condition must be satisfied that the features are clearly shown in the drawings originally filed and are clearly, unmistakably and fully derivable from the drawings in terms of structure and function by a person skilled in the art to enable him to recognise these features as forming part of the invention when considering the content of the description as a whole" (see point 2.2, second paragraph, of the reasons). In the present case, these conditions are met. Indeed, feature (9) is clearly shown in the original Figures 3A and 4, as the Examining Division itself found (see above). Moreover, it is clear to the skilled person that the function of the barrier layer is to act as a physical barrier to prevent precipitation of silicon atoms from an Al-Si metallization film at an ohmic contact with a silicon substrate (see the application, page 5, lines 3 to 12). In order for this function to be fulfilled, the barrier layer should be formed both in the contact hole and around the periphery thereof, as shown in Figures 3A and 4. It is undisputed that no indication is given in the application as filed that feature (9) also improves the adhesion of the barrier layer to the underlying silicon substrate. This is, however, a secondary effect achieved by the invention, irrelevant for the assessment of the admissibility of the amendment under Article 123(2) EPC. In fact, even without being aware of such an effect, the skilled person would be able to recognise feature (9) as forming part of the invention when considering the content of the description as a whole, the invention concerning the use of the metallization film provided in the memory cell portion in order to form a barrier layer with respect to the Al-Si metallization film provided in the peripheral portion of the semiconductor memory device.

2.3. A further objection under Article 123(2) EPC, raised by the Examining Division, was that, although the amendments concerning the definition of the first and second insulation films have their basis in the embodiments of Figures 3A and 3B, "these amendments have been taken out of their proper context of essential features which are explicitly discussed in the description" (see the decision under appeal, point II.2, page 4, second paragraph). In the Board's judgement, this objection is not well founded either. Pursuant to Article 84 EPC the claims shall define the matter for which protection is sought. This matter is defined in terms of the technical features of the invention (Rule 29(1), first sentence, EPC). In particular, the claim has to state the essential features of the invention (Rule 29(3) EPC), whereby "essential features" means that they solve the technical problem underlying the invention (Rule 27(1)(c) EPC). For the purpose of Article 123(2) EPC, the content of the application as filed includes the drawings, so that features which are contained in the drawings may be used to amend the claims provided the condition defined in the case law of the Boards of Appeal and referred to in point 2.2 above is met. In this respect, a distinction should be drawn between the context of a specific embodiment and that of the invention as claimed, which represents the solution to the stated technical problem. In the Board's judgement, a specific feature which is disclosed in a drawing in the context of a particular embodiment of the invention and which is recognised by the skilled person as being essential to the performance of the invention, in other words necessary for the solution of the problem to which the invention relates, may well be included in a claim without having to introduce any other feature of the particular embodiment in which the specific feature is framed. Whether the other features are required for the object of the embodiment to function is not relevant, because, as stated above, the invention as claimed must only define those features which solve the technical problem. It is not the aim of Article 123(2) EPC to oblige the applicant or the patentee to unduly restrict the extent of protection conferred by a claim by including into the claim features of a drawing (an embodiment) which do not contribute to the solution of the problem.

In the present case, only one preferred embodiment of the invention is represented in Figures 2 to 4. All the amendments of claim 1 have a basis in the application as filed and concern essential features of the invention. Moreover, in the Board's judgement, there is no need to introduce any other feature in the amended claim 1.

2.4. Claims 2 to 6 essentially correspond to the original claims 3, and 5 to 8. The subject-matter of claim 7 is disclosed in the application as filed, Figures 2 to 4, page 8, lines 3 to 35, page 12, lines 5 to 19, and page 4, lines 23 to 25.

2.5. The description has been brought into conformity with the amended claims.

2.6. For these reasons, the application meets the requirements of Article 123(2) EPC.

3. Article 84 EPC

There are no objections under Article 84 EPC.

4. Article 54 EPC

4.1. Document D1 concerns a semiconductor memory device as recited in the preamble of claim 1 (see Figure 2). According to Section II, "low resistive TaSi2 on polysilicon is implemented as the gate electrode material." Moreover, "this polycide layer is also used to realize low resistive bit lines" of the memory cells (see Figure 1). In Section VII, it is stated that "high-speed performance was obtained by the extensive use of TaSi2 on source, drain and gate of most NMOS transistors in periphery circuits, on bit lines and also as low resistive interconnects beneath Al lines." This statement in Section VII would not make any technical sense, if the bit lines are considered to be made of polycide according to Section II. In view of the fact that bit lines are conventionally made of doped polysilicon, the expression "bit line" in Section VII can, however, be interpreted as referring to such a conventional polysilicon bit line. Thus, D1 discloses, on the one hand, that in DRAM devices bit lines are used, which are made of a metal silicide film on a polysilicon film, this technical development being acknowledged in the present application on page 5, lines 26 to 31, and page 6, lines 20 to 24, and, on the other hand, that TaSi2, and not polycide, is used as low resistive interconnects beneath Al lines. Hence, there is no mention in D1 that the first metallization film in the memory cell portion, including a refractory metal silicide film on a polysilicon film, further constitutes a barrier layer in the peripheral circuit portion, as specified in the characterising part of claim 1.

4.2. Document D2 (see abstract) addresses the same problem underlying the present application, namely Si precipitation at the contact between Al-Si metallization and silicon. The solution consists in the provision of a thin TaSix (x<2) layer underneath the aluminium-based metallization, which acts as a barrier against silicon precipitation. Attention is also drawn to a statement on page 258, according to which most silicides with low contact resistance react with the top aluminium metallization and thus must be separated from aluminium by an additional diffusion layer. Thus, also D2 does not disclose the feature of claim 1 that the first metallization film in the memory cell portion, including a refractory metal silicide film on a polysilicon film, further constitutes a barrier layer in the peripheral circuit portion.

4.3. For these reasons, the subject-matter of claim 1 is novel, having regard to documents D1 and D2.

5. Inventive step

5.1. An essential feature of the present invention as claimed consists in that the peripheral circuit portion of the semiconductor memory device contains contact holes having a barrier layer formed therein and around a periphery thereof, this barrier layer being constituted by the same metallization film which is used for bit lines in the memory cell portion and has a dual-layer stacked structure of a polysilicon layer and a metal silicide layer. Thus, the invention is based on the idea of providing a barrier layer made of the same polycide structure which is used for bit lines, i.e. with a different function, in a different region of the device. This is possible because the peripheral circuit portion does not employ bit lines. The above idea is not obvious to a skilled person, having regard to the cited documents.

Both D1 and D2 teach away from the present invention. Indeed, as shown above (see points 4.1 and 4.2), their teaching is the use of a single layer of metal silicide as a barrier layer, in particular TaSi2 according to D1 and TaSix according to D2. Document D2 also envisages the possibility of a double layer to solve the same problem as the present invention, i.e. silicon diffusion at the contacts of the Al-Si metallization with shallow diffusion regions in silicon. However, such double layer is different from the claimed polycide structure because it comprises a metal silicide and a diffusion barrier between the silicide and the top aluminium metallization.

Moreover, there would be no reason for the skilled person to think that the polycide structure used for bit lines would also be suitable for making a barrier layer, bearing in mind that bit lines must provide good conduction of charge to and from memory cells whereas barrier layers have to prevent diffusion between adjacent layers. Indeed, these requirements are quite different, so that the skilled person would not consider that the bit line structure could provide a more effective barrier layer.

5.2. The Examining Division's argumentation concerning inventive step (see point II.5.1 of the decision under appeal) is based on the allegation that "D1 teaches the skilled person that the silicide layer of the polycide metallization film is necessary for forming a barrier between silicon and an aluminium based metallization." As a matter of fact, the structure of the peripheral circuits is not disclosed in document D1. It is only stated that the material TaSi2 can be used for bit lines and also as low resistive interconnects beneath Al lines. This disclosure is, however, not sufficient for alleging that "the silicide layer which is used in the polycide film of the bit lines ... has also to be used in the same level of metallization also in the contact hole structures of the peripheral circuit portion", as the Examining Division does. It thus appears that the Examining Division interprets the insufficient disclosure of a prior art document with foreknowledge of the invention with the consequence that an ex post facto analysis results.

5.3. For these reasons, the subject-matter of Claim 1 involves an inventive step, having regard to documents D1 and D2.

6. Since the application and the invention to which it relates meet the requirements of the EPC, a European patent can be granted.